A compact radar antenna has two jobs that can work against each other: radiate efficiently toward the scene, and keep the transmitter from coupling directly into the receivers. A wide impedance bandwidth alone does not solve the second problem. The package, feed structures, polarization, and spacing all influence the leakage paths.
This walkthrough develops a simulated 60 GHz antenna-in-package (AiP) array with one transmit element and three receive elements. It combines an L-probe-fed patch element with increased spacing, orthogonal transmit/receive polarization, and an L-shaped via fence. The focus is the design process: establish a baseline, change one mechanism at a time, and verify matching, coupling, and radiation together.
Scope: this walkthrough presents electromagnetic simulation results and a reusable design method. Fabricated-module measurements and a complete manufacturing specification are outside its scope.
1. Define the bandwidth and isolation targets
The intended radar band is 57–64 GHz. The antenna element is based on a published design with a wider simulated matching band of 56–67 GHz, providing useful frequency margin. Use port 1 for Tx and ports 2–4 for Rx when interpreting the coupling plots.
Quantity
Design objective
What to check
Port matching
Sii < −10 dB
All four ports over the intended band
Tx–Rx isolation
> 30 dB
All three transmit-to-receive paths
Rx–Rx isolation
> 20 dB
Every receive-port pair
Element gain
> 5 dBi
Useful broadside radiation without a split main beam
Architecture
1 Tx + 3 Rx
A compact 2 × 2 physical arrangement
Design targets for the 1T3R array, including a 20 dB Rx–Rx isolation objective.
Be precise about the sign convention. A coupling trace of −30 dB corresponds to 30 dB of isolation, not “negative isolation.” With the other ports matched:
At 60 GHz, the free-space wavelength is approximately 5 mm. That makes millimeter-scale layout changes electrically significant:
For an ideal FMCW radar, the swept signal bandwidth sets range resolution. A 7 GHz sweep gives approximately 2.14 cm; an 11 GHz sweep gives approximately 1.36 cm. Antenna bandwidth makes such a sweep possible, but does not by itself establish the usable bandwidth of the complete radar.
2. Start from the referenced L-probe-fed element
The antenna element is adapted from “Wideband L-Probe Fed Antenna-in-Package Module for Millimeter-Wave Radar”, presented at the 2024 IEEE Conference on Antenna Measurements and Applications (CAMA). The element topology and baseline bandwidth come from that reference; the 1T3R arrangement and hybrid decoupling study discussed here are the subsequent project work.
The referenced element has three main parts: a rectangular radiating patch, an L-shaped feed probe, and a metal-backed cavity. Its HDI stack-up uses five dielectric layers and six metal layers, with relative permittivity 3.5, 250 μm core layers, 50 μm prepreg layers, and 18 μm metallization. These are reference-design parameters, not a complete manufacturing specification for this array.
The vertical probe contributes inductive reactance. Its horizontal arm couples capacitively to the patch, providing another tuning degree of freedom. A useful first-order picture is:
This equivalent circuit explains the tuning direction; it does not replace a full-wave model of the coupled patch and probe. Sweep patch dimensions, horizontal probe length, and probe-to-patch separation while watching the entire matching band. The cavity and its via walls also shape substrate fields and back radiation.
The reference reports a 56–67 GHz simulated impedance bandwidth. Using the arithmetic band center gives:
Do not confuse the two rotation strategies: the reference explores rotating both antennas by 45° relative to their layout; this project rotates the Tx element by 90° relative to the Rx elements to introduce orthogonal polarization.
3. Build the 1T3R layout
Arrange the elements in a 2 × 2 footprint. In the project development, the element spacing increased from 3.0 mm to 5.0 mm before adding polarization and via-fence decoupling. At 60 GHz those distances are approximately 0.6λ0 and 1.0λ0. More spacing changes the coupling environment, but also consumes package area.
Rotate the Tx patch and feed together by 90°; retain the original orientation for all three Rx elements. Then place an L-shaped metal via fence between the Tx region and its adjacent receive regions. Preserve electrical connections to the intended metal planes, and check that the fence does not intersect feeds or disturb the individual cavity boundaries.
Figure 1. Array top view. The upper-left element is rotated by 90°. The Chinese annotation identifies the isolation wall.Figure 2. Perspective view of the multilayer array, showing the feeds, cavity boundaries, and additional via fence.
4. Assign a job to each decoupling mechanism
Spacing changes the field strength and phase seen by neighboring elements. Keep it fixed when comparing the other two mechanisms, otherwise an apparent improvement cannot be attributed cleanly.
Orthogonal polarization reduces coupling between differently oriented fields. For two ideal linearly polarized plane waves, polarization overlap follows:
The ideal overlap is zero at 90°, but a compact packaged array is not a pair of ideal plane waves. Near fields, finite cross-polarization, shared grounds, and substrate paths leave residual coupling. Orthogonal Tx/Rx polarization can also reduce the desired echo from polarization-preserving targets, so port isolation must eventually be checked against the radar link budget and target scattering behavior.
The via fence modifies the substrate-field paths and acts approximately as a conducting boundary. Its effectiveness depends on via diameter, pitch, height, plane connections, and placement. A simple pitch smaller than half a wavelength is not sufficient to guarantee a good wall: use the relevant dielectric or guided wavelength, account for the gap between vias, and confirm the result with full-wave fields and S-parameters.
The mechanisms interact. Adding a fence can improve one frequency region while introducing ripple elsewhere. Optimize the worst-case response across the band rather than the depth of one attractive isolation notch.
5. Set up a controlled simulation sequence
Use the following workflow to compare the decoupling mechanisms in a full-wave solver:
Validate one element. Include the stack-up, finite conductivity, dielectric loss, feed, and cavity. Establish matching and broadside radiation before building the array.
Create the spaced array. Start with the same element geometry and a fixed 5.0 mm spacing. Use consistent port definitions and reference planes.
Compare polarization. Evaluate co-polarized and orthogonal arrangements without the added fence. Keep the remaining geometry and solver settings fixed.
Add the fence. Compare the orthogonal arrangement with and without the L-shaped via fence. Inspect substrate fields as well as port coupling.
Check every port. Excite one port at a time with the others matched. Evaluate all four reflections, three Tx–Rx paths, and three Rx–Rx pairs.
Resolve narrow resonances. Sweep 50–70 GHz for context, refine the frequency sampling near peaks, and verify mesh convergence around probes, gaps, and vias. Repeat far-field checks near the band edges and center.
Record the mesh, loss models, and convergence settings so that each comparison can be reproduced.
6. Read the matching and coupling results
Figure 3. Simulated port reflections. The curves support an approximately 56–67 GHz band at the −10 dB threshold; they are not below −15 dB over that entire interval.
The four reflection curves track closely. They show a broad matched region and a deeper minimum near 64 GHz. Extract each threshold crossing from numerical data before reporting exact bandwidth: the image supports an approximate band, not sub-gigahertz endpoint precision.
Figure 4. Tx–Rx coupling for the hybrid layout. More negative values indicate better isolation.
The displayed Tx–Rx traces remain below −30 dB, supporting the 30 dB objective. Local coupling peaks approach −32 dB, so the plots do not establish a strict 33 dB minimum isolation at every frequency.
Figure 5. Rx–Rx coupling for S24 and S23. The worst displayed coupling is approximately −26 dB.
The shown receive-port paths exceed the 20 dB isolation objective. However, this figure does not show every Rx–Rx pair in the final layout. Do not assume the missing path is identical unless symmetry or the full S-matrix establishes it.
7. Separate polarization and fence effects
Figure 6. No-fence comparison at fixed spacing: the red solid curve is the orthogonal pair and the blue dashed curve is the co-polarized pair.
Over much of the intended band, the orthogonal pair has lower coupling, with roughly 5 dB improvement in several regions. Near 67 GHz the co-polarized trace approaches −28 dB. The curves cross at the low end of the wider sweep, so polarization is not uniformly better at every plotted frequency. Also, this comparison uses different port pairs; a stricter attribution experiment would rotate the same pair while holding all other geometry fixed.
Figure 7. Fence comparison. Solid traces include the fence; dashed traces omit it. The axis label “Isolation” uses negative coupling-in-dB values.
The no-fence red trace rises to about −27 dB near 67.5 GHz, outside the intended 57–64 GHz radar band and just above the reference matching band. The fence suppresses this high-frequency deterioration. That is useful evidence of additional margin, but should not be described as a failure inside the intended band. Elsewhere, ripple and notches move in both directions: the benefit is frequency-dependent.
8. Check radiation before accepting the design
Low coupling is not enough if the antenna loses useful gain or sends energy away from the target. The simulation results give approximate peak gains of 5.8 dBi for Tx and 5.9 dBi for Rx, with broadside main beams and a front-to-back ratio greater than 20 dB. The polar plots below illustrate the radiation shape; their frequency and trace labels are insufficient to independently verify each numerical value.
Figure 8. E-plane radiation cut.Figure 9. H-plane radiation cut. Individual traces are not assigned to Tx or Rx without an identifying legend.
For a final design review, export realized gain, radiation efficiency, co- and cross-polarized cuts, and front-to-back ratio for every active port at clearly stated frequencies. Follow this with a radar-level test that includes the target’s polarization response. An isolation improvement is only useful if the desired echo remains detectable.
9. What this design demonstrates
The most reusable lesson is to treat antenna isolation as a combination of paths. Spacing changes the interaction geometry; polarization reduces some direct coupling; the via fence reshapes substrate and near-field paths. The simulations support a wide matched band, Tx–Rx isolation above the 30 dB design objective in the displayed sweep, and approximately 26 dB or better isolation for the receive pairs shown.
Before fabrication, complete the dimensioned stack-up and feed definition, verify the full S-matrix with converged numerical data, sweep manufacturing tolerances, and account for packaging and material losses. The present figures provide a useful design study, not measured proof of radar sensitivity or a guarantee across process variations.
Analog IC design does not end when the schematic meets its specifications. The circuit must survive its translation into geometry: matched devices need matched environments, high-impedance nodes need short and quiet routes, power paths need low resistance, and every shape must satisfy the process design rules. This tutorial walks through that complete flow using a Miller-compensated two-stage CMOS operational amplifier, followed by a non-inverting gain-of-two application with pads and ESD protection.
The emphasis is not on one particular PDK. Instead, the goal is to show a reusable way to move from specifications to transistor sizing, pre-layout verification, matching-aware layout, DRC/LVS/PEX, and post-layout sign-off.
1. Define the design target
The example uses a 1.8 V, 0.18 µm CMOS process. The open-loop amplifier is designed around the following targets:
Metric
Target
Why it matters
DC open-loop gain
≥ 80 dB
Reduces closed-loop gain error
Unity-gain frequency
≥ 1 MHz
Sets the useful closed-loop bandwidth
Typical phase margin
≥ 60°
Provides a well-damped transient response
Corner phase margin
≥ 45°
Maintains stability across PVT variation
Power
As low as practical
Constrains branch currents and device sizes
A useful habit is to keep the specification table visible throughout the project. Every sizing choice, simulation, and layout compromise should map back to one or more rows in this table.
A classic two-stage architecture is a strong starting point when high DC gain and a reasonably large output swing are required:
First stage: an NMOS differential pair (M1 and M2) with a PMOS current-mirror load (M3 and M4). This stage provides differential-to-single-ended conversion and much of the voltage gain.
Second stage: a PMOS common-source device (M6) with an NMOS current-source load (M7). It adds gain and improves output swing.
Bias network: a diode-connected NMOS reference device (M8) biases the first-stage tail source M5 and the second-stage load M7.
Frequency compensation: a Miller capacitor, Cc, connects the first-stage output to the amplifier output and separates the dominant and non-dominant poles.
At zero differential input, the tail current divides equally:
The topology is intentionally simple. Simplicity helps both electrically and physically: fewer internal nodes reduce parasitic uncertainty, and a regular device structure is easier to match in layout.
3. Establish the current plan before sizing devices
Start with a 10 µA reference current. Mirror ratios then establish the branch currents:
M8 carries 10 µA.
M5 uses a 2× ratio and supplies 20 µA to the input pair, or approximately 10 µA per side at zero differential input.
M7 uses an 8× ratio and biases the second stage at approximately 80 µA.
The second stage deliberately receives more current than either half of the input stage. Its higher transconductance pushes the non-dominant pole upward and gives the output node more drive capability.
The final device set used in this case study is:
Device
Type
Unit W/L (µm/µm)
Multiplier
Approx. current
M1, M2
NMOS input pair
2.25/1
2
10 µA each
M3, M4
PMOS mirror load
9/1
1
10 µA each
M5
NMOS tail source
4.5/1
2
20 µA
M6
PMOS second stage
4.5/1
16
80 µA
M7
NMOS second-stage load
4.5/1
8
80 µA
M8
NMOS bias reference
4.5/1
1
10 µA
Cc
MIM capacitor
—
—
4.5 pF
Longer-than-minimum channel lengths are useful here because they improve output resistance, intrinsic gain, and matching. The cost is area and parasitic capacitance, so the choice should always be verified in simulation.
4. Use first-order equations to guide simulation
For a long-channel MOS device in saturation, a useful first-order transconductance estimate is:
For a Miller-compensated two-stage op-amp, the gain-bandwidth product is approximately:
With an input-device transconductance near 101 µS and Cc = 4.5 pF, the first-order estimate is about 3.57 MHz. This clears the 1 MHz requirement with margin. The simulated result is higher because the compact hand calculation ignores several second-order effects.
The second-stage transconductance is approximately 792 µS—almost eight times gm1:
That ratio is helpful because the non-dominant pole roughly tracks the second-stage transconductance divided by its load capacitance:
A stronger second stage therefore makes it easier to maintain phase margin after compensation.
These equations are not substitutes for transistor-level simulation. Their job is to establish a sensible starting point and to explain why a later simulation result moves in a particular direction.
5. Verify the schematic before drawing layout
Run the following checks before opening the layout editor:
DC operating point: confirm every MOS device is in saturation over the intended common-mode and output ranges.
Open-loop AC or stability analysis: measure low-frequency gain, UGF, and phase margin.
PVT corners: include slow/high-temperature/low-voltage and fast/low-temperature/high-voltage extremes.
Closed-loop transient tests: check settling, distortion, and slew rate at the intended noise gain.
Noise: identify which devices dominate the input-referred noise.
At the typical corner, the open-loop simulation produced 84.95 dB of gain, a 4.56 MHz UGF, and 66.44° of phase margin. The slow corner reached 3.79 MHz with 67.22°, while the fast corner reached 5.83 MHz with 65.43°. All three cases met the target.
For the closed-loop DC operating point, the measured total current was about 111.1 µA, giving:
Figure 2. Typical-corner open-loop gain and phase response.
6. Translate electrical intent into a floorplan
Layout should begin with a placement plan, not with routing. Group devices by matching requirement and signal sensitivity:
6.1 Differential pair
Split M1 and M2 into equal fingers and use a two-dimensional common-centroid pattern such as:
D M1 M2 D
D M2 M1 D
This arrangement averages both horizontal and vertical process gradients. Keep the source connections, gate routes, drain loading, contacts, and surrounding dummy environment as symmetric as possible. Common-centroid placement does not help if the routing destroys the symmetry.
6.2 PMOS mirror and second-stage device
Place the matched PMOS load devices near the center of a shared well. An A-B-B-A arrangement gives M3 and M4 a similar neighborhood. The large M6 device can be split into two equal groups and placed symmetrically around the matched pair so that its area does not force a one-sided floorplan.
6.3 NMOS current mirrors
Place the reference device M8 centrally, put the two M5 halves close to it, and distribute the M7 fingers symmetrically toward the outside. Equalize gate routing from the bias node and use the same contact style on every mirror member.
6.4 Compensation capacitor
Keep the MIM capacitor away from noisy digital or large-swing routes. More importantly, keep both of its connections short: one terminal touches the sensitive first-stage output, while the other connects to the amplifier output. Excess parasitic capacitance on the first-stage node directly changes the pole-zero locations.
Figure 3. Amplifier core layout with the MIM capacitor and matched device arrays.
7. Route in order of sensitivity
A practical routing order is:
Matched differential and mirror connections.
The first-stage high-impedance output and both compensation-capacitor terminals.
Bias lines.
Output path.
Power and ground.
Use wider metal and dense via arrays for supply and output paths. Keep high-impedance routes short, avoid running them parallel to large-swing nets, and add shielding only when the shield can be tied to a genuinely quiet node. A poorly chosen shield can add more capacitance than the coupling it removes.
8. Close the DRC–LVS–PEX loop
8.1 DRC is more than a final checkbox
Run DRC incrementally. In this layout, two representative violations were minimum Metal 1 spacing in a dense local route and insufficient spacing on the top metal near a power or capacitor connection. Both were fixed by replanning the route rather than applying a cosmetic patch.
When a fix changes symmetry, immediately check its matched counterpart. A geometrically legal asymmetry can still create an analog error.
Figure 4. DRC verification of the completed op-amp core layout.
8.2 LVS checks connectivity, not performance
A clean LVS result confirms that layout and schematic have the same devices and nets. It does not confirm matching quality, current density, antenna robustness, or stability. Treat LVS as one layer of evidence, not as the definition of a good layout.
8.3 PEX exposes naming and parasitic mistakes
After LVS, extract resistance and capacitance, including coupling capacitance. A subtle but common failure is inconsistent terminal naming. In this case, mixed-case input labels in the schematic did not match uppercase layout pins. Renaming the schematic pins consistently allowed the extracted view to netlist correctly.
This is a useful debugging rule: when PEX reports a netlist mismatch after LVS is clean, inspect view selection, terminal direction, bus syntax, hierarchy, and case sensitivity before redrawing geometry.
9. Compare pre-layout and post-layout results
Post-layout simulation should use the same testbenches, measurements, corners, and plotting conventions as pre-layout simulation. Otherwise, the comparison is ambiguous.
Metric
Pre-layout
Post-layout
Change
Open-loop gain
84.95 dB
84.92 dB
−0.03 dB
Unity-gain frequency
4.56 MHz
4.46 MHz
−0.10 MHz
Phase margin
66.44°
66.37°
−0.07°
The small UGF reduction is expected: routing adds capacitance to internal high-impedance nodes. The important result is not that the values are identical, but that the degradation is small, explainable, and still leaves comfortable specification margin.
10. Turn the op-amp into a practical gain-of-two block
To verify the amplifier in a realistic closed-loop configuration, connect it as a non-inverting amplifier with equal feedback and ground resistors:
Use equal resistor geometry and place the two functional resistors in the same array. A simple pattern is:
Dummy Rf Rg Dummy
The dummies make the etch and stress environment of the two functional resistors more similar. Ratio accuracy matters more than absolute resistance because the closed-loop gain depends on Rf/Rg.
The 10 kΩ value is also a compromise between output loading and resistor noise. The resistor’s thermal-noise voltage density is:
Very small resistors unnecessarily load the output, while very large resistors increase thermal noise and create lower-frequency poles with parasitic capacitance.
Figure 5. Closed-loop gain-of-two application with ESD interfaces and feedback resistors.
The pre-layout closed-loop simulation produced 6.038 dB of gain, very close to the ideal 6.02 dB, with a −3 dB bandwidth of 1.979 MHz. A DC sweep identified approximately 0.6 V as a useful common-mode bias point for the largest linear output range.
Figure 6. Closed-loop DC sweep of output voltage and dVout/dVin.Figure 7. Closed-loop AC magnitude response.
11. Add pads, ESD, and top-level routing
The top-level layout integrates the op-amp core, feedback network, I/O protection, and pads. Place the sensitive core and feedback resistors near the center. Arrange signal and supply pads around the perimeter, and provide short, low-impedance discharge paths from each ESD cell to the supply rails.
A wide power ring and generous via arrays reduce both normal IR drop and transient ESD impedance. Avoid routing a protected signal through a long narrow path after the clamp; that inductive and resistive segment can defeat the intended protection during a fast event.
Figure 8. Top-level layout integrating the analog core, resistor array, ESD cells, pads, and power routing.
12. Measure the cost of pads and extraction
After extracting the complete top level, compare it with the schematic-level application:
Metric
Pre-layout
Post-layout
Interpretation
Closed-loop gain
6.038 dB
6.040 dB
Resistor ratio preserved
−3 dB bandwidth
1.979 MHz
1.940 MHz
About 2% reduction
Slew rate
1.398 V/µs
1.377 V/µs
Small parasitic penalty
Integrated input-referred noise
96.57 µV RMS
96.43 µV RMS
Essentially unchanged
Figure 9. Pre-layout and post-layout AC responses showing the extracted-parasitic bandwidth shift.
The noise report also illustrates how schematic abstractions map to physical devices. A transistor represented with a multiplier of two can appear after extraction as two parallel finger devices. Their individual noise contributions may be reported separately, but their sum should remain close to the original device contribution. This is expected behavior, not a new noise source.
13. A reusable sign-off checklist
All critical devices remain in the intended operating region across PVT.
Typical and worst-case gain, bandwidth, phase margin, power, noise, and slew rate meet the specification.
Matched devices have equal geometry, orientation, contacts, routing, and edge environment.
High-impedance nodes are short and isolated from large-swing routes.
Supply and ESD paths use adequate width and via density.
DRC is clean at both block and top level.
LVS is clean with the intended hierarchy and device parameters.
PEX includes the required resistance, capacitance, and coupling models.
Post-layout tests reuse the pre-layout benches and measurement definitions.
Every performance shift has a plausible physical explanation and sufficient remaining margin.
Conclusion
The central lesson of analog layout is that geometry is part of the circuit. Common-centroid placement, dummies, symmetric routing, careful pole-node wiring, ratio-matched resistors, and low-impedance pad protection are not aesthetic choices—they determine whether the schematic behavior survives fabrication.
In this example, the extracted open-loop UGF changed from 4.56 MHz to 4.46 MHz, and the complete gain-of-two block lost less than 2% of its bandwidth after pads and ESD were included. Those small, predictable shifts are the reward for treating layout constraints as part of the electrical design from the beginning.
