Analysis and Design of Operational Transconductance Amplifiers (OTAs)

In this post, we will walk through the systematic design and simulation of Operational Transconductance Amplifiers (OTAs) using the GlobalFoundries $0.18\mu m$ BCDlite process. We will cover the topology, working principles, and frequency compensation techniques for two classic architectures: the Two-Stage Miller Compensated OTA and the Folded-Cascode OTA.

By the end of this guide, you will understand how to translate circuit specifications (Gain, Bandwidth, Slew Rate) into small-signal parameters ($g_m$, $r_o$), determine transistor dimensions, and verify your design using Cadence Virtuoso.

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Part 1: Two-Stage Miller Compensated OTA Design

Our first design is a two-stage Miller compensated OTA featuring an NMOS differential input stage and a PMOS common-source second stage. We use a Miller capacitor ($C_C$) for frequency compensation and a series nulling resistor ($R_Z$) to eliminate the effect of the right-half-plane (RHP) zero.

1.1 Slew Rate (SR) and Load Driving Capability

We start by determining the tail current and compensation capacitor based on the Slew Rate (SR) and load capacitance requirements.

• Design Target: $SR \ge 5 V/\mu s$
• Design Process:
  For a two-stage OTA, the Slew Rate is typically limited by the charging/discharging speed of the Miller capacitor $C_C$ (limited by the first-stage tail current) or the load capacitor $C_L$ (limited by the second-stage output current). The empirical formula is:
  $$SR = \frac{I_{tail}}{C_C}$$
  Considering Phase Margin (PM) requirements, we usually select $C_C \approx (0.2 \sim 1)C_L$. Given a load $C_L = 2pF$, and ensuring $C_C$ isn’t too small to avoid parasitic effects, we select:
  Final Value: $C_C = 1.58pF$. Substituting this into the SR formula to find the required tail current ($I_{tail}$):
  $$I_{tail} = SR \times C_C = 5V/\mu s \times 1.58pF \approx 7.9\mu A$$
  To leave enough margin and improve bandwidth, we design the tail current to be significantly larger than the theoretical minimum. We use a reference current $I_{ref} = 9\mu A$ and a current mirror ratio of 1:6, resulting in a first-stage tail current of $54\mu A$. This yields a theoretical SR of $\approx 34 V/\mu s$, far exceeding the target.

1.2 Determining Input Transconductance ($g_{m1}$)

• Design Target: Gain-Bandwidth Product ($GBW \ge 10MHz$)
• Design Process:
  The Unity Gain Bandwidth (UGF or GBW) is approximately: $$\mathrm{GBW}\approx \frac{g_{m1}}{2\pi C_C}$$
  Working backwards from the requirement: $$g_{m1}\ge \mathrm{GBW}\times 2\pi C_C=10\mathrm{MHz}\times 2\pi \times 1.58\mathrm{pF}\approx 99.2\mu S$$
  With a single-branch current $I_{D1}=I_{\mathrm{tail}}/2=27\mu A$ and NMOS process parameter $K_n\approx 113.4\mu A/V^2$ , we use the transconductance formula $g_m=\sqrt{2K_n(W/L)I_D}$ to size the input transistors (M1, M2). To maximize gain, we choose a large channel length: $L=8\mu m$ and $W=30\mu m$ ($W/L=3.75$).
  The estimated $g_{m1}$ is $\approx 151\mu S$ , yielding a GBW of $\approx 15.2\mathrm{MHz}$, satisfying the $>10\mathrm{MHz}$ requirement.
  (For educational simplicity, we are using excessively long channel lengths to achieve high gain. In a practical industry setting, a designer would utilize a cascode topology rather than wasting silicon area.)

1.3 Boosting Low-Frequency Voltage Gain

• Design Target: DC Open-Loop Gain $A_{v0} \ge 90dB$
• Design Process:
  The total gain is the product of the first-stage differential gain and the second-stage common-source gain: $$A_{v0}=A_{v1}\times A_{v2}\approx \left[g_{m1}\right(r_{o2}\parallel r_{o4}\left)\right]\times \left[g_{m6}\right(r_{o6}\parallel r_{o7}\left)\right]$$
  Since $g_m\propto \sqrt{W/L}$ and $r_o\propto L/I_D$ , the intrinsic gain $g_m{r}_o\propto \sqrt{WL}$ . To achieve >90dB (a voltage multiplier of >31622) without using a cascode structure, we must significantly increase the channel length $L$ to minimize channel length modulation ( $\lambda$ ) and boost the output resistance $r_o$ .
  • First Stage: We set $L_{1,2,3,4}=8\mu m$ . This pushes $r_{o2}$ and $r_{o4}$ into the Mega-ohm ( $M\Omega$ ) range.
  • Second Stage: To provide gain while driving the load, we set $L_{6,7}=4\mu m$ .
  • Estimated Gain: $A_{v1}\approx 50\sim 55\mathrm{dB}$ , $A_{v2}\approx 40\sim 45\mathrm{dB}$ , totaling $>90\mathrm{dB}$ .

1.4 Second-Stage Transconductance ($g_{m6}$) and Nulling Resistor ($R_Z$)

• Design Target: Phase Margin (PM) $> 60^\circ$
• Design Process:
  For stability, the non-dominant pole $p_2 \approx g_{m6}/C_L$ must be far from the GBW (typically $p_2 \ge 2.2 \times GBW$). Furthermore, the RHP zero $z = g_{m6}/C_C$ degrades PM and must be mitigated using a nulling resistor $R_Z$.
  We set the second-stage bias current to $126\mu A$ and size PMOS M6 as $W/L = 100\mu m / 4\mu m = 25$.
  Theoretically, $R_Z \ge 1/g_{m6}$. Through parametric sweeps, we optimize the nulling resistor to $R_Z = 12k\Omega$.

1.5 Component Sizing Summary

Module	Component	Type	W ( $\mu m$)	L ( $\mu m$)	Bias / Value
Bias Current	$I_{DC}$	Current Source	–	–	$9\mu A$
Bias Mirror	M8	NMOS	4	4	Reference
Diff. Input	M1, M2	NMOS	30	8	$g_{m1}$ Core
Active Load	M3, M4	PMOS	44	8	Boost $r_o$
Tail Current	M5	NMOS	24	4	$I_{\mathrm{tail}}=54\mu A$
2nd Stage Amp	M6	PMOS	100	4	CS Stage
2nd Stage Load	M7	NMOS	56	4	$I_{stg2}=126\mu A$
Comp. Network	$C_C$	Capacitor	–	–	$1.58\mathrm{pF}$
Nulling Res.	$R_Z$	Resistor	–	–	$12k\Omega$

[Figure 1: Schematic of the Two-Stage Miller Compensated OTA]

1.6 Simulation Results (Two-Stage OTA)

DC Operating Point and Power

With $V_{DD} = 5V$ and $V_{ICM} = 2.5V$, the total static current is $184.52\mu A$. Total power consumption is roughly $0.92 mW$, well below the $1 mW$ constraint. All critical transistors operate in the deep saturation region.

[Figure 2: DC Operating Point of Unity-Gain Buffer]

Stability Analysis (STB)

• DC Loop Gain: 105.24 dB (Exceeds 90dB target due to long-channel devices).
• GBW: 10.94 MHz.
• Phase Margin (PM): $60.79^\circ$. The nulling resistor successfully pushes the RHP zero away, ensuring stability. PM can be read directly on the STB Summary Window.

[Figure 3: STB Analysis Amplitude and Phase Plot]

[Figure 4: STB Analysis Summary Window]

AC Analysis (Open-loop and Closed-loop)

When configured as a unity-gain buffer, the closed-loop -3dB bandwidth is measured at 17.15 MHz. Since our system acts as a second-order system with PM $\approx 60^\circ$, peaking causes the closed-loop -3dB bandwidth to extend beyond the open-loop UGF (theoretically $f_{-3dB} \approx 1.6 \times UGF$).

[Figure 5: AC Open Loop Response]

[Figure 6: AC Closed Loop Response]

Transient Response and Slew Rate

Testing with a 250kHz square wave and $C_L = 2pF$, the output tracks smoothly without obvious ringing, verifying excellent phase margin.

• Measured SR: $24.25 V/\mu s$ (Significantly better than the $5 V/\mu s$ target).

[Figure 7: Transient Analysis and Slew Rate]

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Part 2: Two-Stage OTA with a Folded-Cascode First Stage

The second design explores a Folded-Cascode OTA. This topology combines the high-gain characteristics of a cascode stage with the wide input common-mode range of a folded structure.

2.1 Core Topology and Bias Strategy

• Input Stage: We use a PMOS differential pair (PM4, PM5). Signal current flows out of the PMOS drains into the folding nodes.
• Folding Branch & Cascode Load:
  • Upper PMOS Cascode: Acts as the main current source and provides extremely high output impedance looking upwards ($R_{up} \approx g_m r_o^2$).
  • Lower NMOS Folded Cascode: The signal current is injected into the source of the cascode devices. This matches the upper impedance, guaranteeing massive first-stage gain.
• Bias Network: We employ a Wide-Swing Cascode Bias circuit to generate bias voltages, ensuring maximum output voltage swing.
• Current Distribution: The tail current is set to $20\mu A$, split equally ($10\mu A$ each) through the input pair. The folding branch is biased at $20\mu A$. Therefore, the static current flowing through the lower NMOS cascode stack is $20\mu A – 10\mu A = 10\mu A$. This ensures devices do not turn off during large-signal swings, maintaining a high slew rate. Total power consumption is calculated at $\approx 0.6 mW$.

2.2 Gain and Frequency Compensation

• High Gain Realization: The output impedance at the first stage is the parallel combination of PMOS and NMOS cascode impedances. Even with short channel lengths ($L = 1\sim 2\mu m$), the first-stage gain easily exceeds 60dB. Combined with a second common-source stage, total gain reaches well over 90dB.
• Compensation: We utilize Miller compensation ($C_C = 1pF$) for pole splitting and a nulling resistor ($R_Z = 8k\Omega$) to boost PM above $60^\circ$.
• Slew Rate: Determined by the tail current: $SR = I_{tail} / C_C = 20\mu A / 1pF = 20 V/\mu s$.

2.3 Component Sizing Summary (Folded Cascode)

Module	Component	Type	W ($\mu m$)	L ($\mu m$)	Function
Bias Gen	NM0-NM3	NMOS	16	1	Wide-swing bias
Bias Ref	PM0, PM1	PMOS	20	2	Bias reference
Tail Current	PM2, PM3	PMOS	40	2	$20\mu A$ tail current
Input Pair	PM4, PM5	PMOS	100	1	Core transconductance
Upper Fold	PM6, PM10	PMOS	40	2	Main current source
Cascode Up	PM11, PM12	PMOS	40	2	Impedance boost
Lower Fold	NM4, NM5	NMOS	59.025	1	Signal fold / CG stage
Current Src	NM6, NM7	NMOS	59.025	1	Bottom current source
2nd Stage	NM8	NMOS	80	1	CS Amplifier
2nd Stage Ld	PM13	PMOS	100	2	Active Load
Comp. Net	Cc	Cap	–	–	1 pF
Nulling Res	Rz	Res	–	–	8 kΩ

[Figure 8: Schematic of the Folded-Cascode OTA]

2.4 Simulation Results (Folded-Cascode OTA)

DC Analysis

Total current is $130.48 \mu A$ (Power $\approx 0.65 mW$). The output DC voltage is naturally stabilized near 2.5V, indicating minimal systematic offset and excellent current mirror matching.

[Figure 9: DC Operating Point of Folded-Cascode OTA]

Stability Analysis (STB)

• DC Loop Gain: 115.1 dB. The cascode structure allows for extreme gain (>110dB) even with short channel lengths, significantly outperforming the standard two-stage OTA.
• GBW: 39.5 MHz. The high transconductance of the input pair ($g_m \approx 137\mu S$) and smaller compensation cap ($C_C = 1pF$) yield an impressive bandwidth.
• Phase Margin (PM): $69.2^\circ$. An exceptionally safe and optimal value, ensuring smooth transient settling without overshoot.

[Figure 10: STB Analysis of Folded-Cascode OTA]

[Figure 11: AC Open Loop Analysis]

AC Closed-Loop Response

When configured as a unity-gain buffer, the closed-loop -3dB bandwidth stretches to 81.24 MHz (roughly $2\times$ the open-loop UGF). This highlights the superior high-frequency capabilities of the folded-cascode architecture.

Transient Response and Slew Rate

The output perfectly tracks the 250kHz square wave. The rising/falling edges are incredibly clean with zero visible ringing, perfectly reflecting the $69^\circ$ phase margin.

• Measured SR: $13.8 V/\mu s$.

(Note: The measured SR is slightly lower than the theoretical $20V/\mu s$. This is due to parasitic capacitances at the folding nodes absorbing some charging current, and dynamic shifts in the operating point during large-signal swings. However, $13.8V/\mu s$ is still excellent for a 0.65mW amplifier).

[Figure 12: Transient Analysis and Slew Rate of Folded-Cascode]

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Part 3: Deep-Dive Analog Design Concepts

Based on the experiments above, here are three critical concepts every analog designer must master:

3.1 Poles, Zeros, and Pole-Splitting Mechanism

In a two-stage Miller compensated OTA, the small-signal poles are distributed as follows:

• Dominant Pole (p_1): Located at the first-stage output. Due to the Miller effect, $C_C$ is magnified by $(1+A_{v2})$ at this node.
  $p_1 \approx \frac{1}{R_{out1} \cdot (A_{v2}C_C)} \approx \frac{1}{R_{out1} g_{m2} R_{out2} C_C}$
• Non-Dominant Pole (p_2): Located at the second-stage output.
  $p_2 \approx \frac{g_{m2}}{C_L}$
• RHP Zero ($z$): Caused by the feedforward path through $C_C$.
  $z = \frac{g_{m2}}{C_C}$

The Magic of Pole Splitting:
Before adding $C_C$, the two poles are close together (determined by nodal resistances and parasitics), making the system unstable. Introducing $C_C$ causes a profound effect:

1. p_1 moves to a lower frequency (because the effective capacitance at node 1 becomes massive).
2. p_2 moves to a higher frequency (because at high frequencies, $C_C$ acts as an AC short circuit between the gate and drain of the second stage, effectively dropping its output resistance to roughly $1/g_{m2}$).

This “one goes low, one goes high” effect splits the poles apart, guaranteeing stability and phase margin.

3.2 What Actually Determines Slew Rate?

Slew rate is the maximum rate of change of the output voltage. It is bottlenecked by the charging/discharging of crucial capacitors ($C_C$ or $C_L$).

• The current available to charge $C_C$ is limited by the first-stage tail current ($I_{tail}$).
• The current available to charge $C_L$ is limited by the second-stage output current ($I_{out}$).
• Design Rule: $SR = \min \left( \frac{I_{tail}}{C_C}, \frac{I_{out}}{C_L} \right)$

In our designs, we ensured the second-stage current was sufficiently large, meaning the SR was primarily limited by the Miller capacitance charging rate.

3.3 Choosing the Right $g_m$ Expression for Design

There are three common ways to express transconductance (g_m):

1. $g_m = \sqrt{2 \mu C_{ox} (W/L) I_D}$ (Useful when Bias Current is fixed)
2. $g_m = \frac{2I_D}{V_{OV}}$ (Useful when Overdrive Voltage and Linearity are priorities)
3. $g_m = \mu C_{ox} (W/L) V_{OV}$ (Useful when Bias Voltage is fixed)

Practical Tip: During layout and circuit sizing, the first formula is often the most practical. Why? Because your total current $I_D$ is usually strictly constrained by the project’s power consumption budget (e.g., <1mW). Under a strict power budget, the most direct way to increase bandwidth (which requires increasing $g_{m1}$) is to increase the aspect ratio ($W/L$) of the input transistors.

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Conclusion

In this tutorial, we successfully designed two high-gain OTAs:

1. The Two-Stage Miller OTA: Achieved an impressive 105 dB open-loop gain by utilizing long-channel devices. With precise $C_C$ and $R_Z$ tuning, we secured a $60.8^\circ$ phase margin and a $24.25 V/\mu s$ Slew Rate, all while staying under 0.93 mW.
2. The Two-Stage OTA with a Folded-Cascode First Stage: Demonstrated the power of cascoding by achieving 115 dB gain using short-channel devices (saving layout area). It showcased superior speed with a 39.5 MHz GBW and a closed-loop bandwidth of over 81 MHz, maintaining extreme stability ($69.2^\circ$ PM) at just 0.65 mW.

Both architectures have their unique strengths. Standard two-stage designs are great for high-swing, general-purpose applications, while folded-cascode topologies excel in high-speed, high-gain, and wide common-mode range scenarios.